1. Radar Interface Card – XC2S200E-6PQ208I
- FPGA logic developed for Interference Suppression Algorithm in incoming Radar signals
- FPGA logic developed for Local Bus Management and Bridge between VME bus and Local Bus on card
- Logic developed for multiple video input selection and software gain setting on all the Analog Video inputs
- Logic for Control and Configuration of Peripherals on Card
- VME Slave Bus Controller
2. Radar Video Interface Card – XC2S200E-6PQ208I
- FPGA logic developed for Local Bus Management and Bridge between VME bus and Logic developed for multiple video input selection and software gain setting on all the Analog Video inputs
- Logic for Control and Configuration of Peripherals on Card
- VME Slave Bus Controller
3. Data Recorder Interface – XC2S200E-6PQ208I
- FPGA logic developed for Presence/Absence Detection of Multiple communication channel inputs such as ISDN, PSTN,
- Intercom and Custom Channels
- Logic for Control and Configuration of Peripherals on Card
- Logic for Keypad scanning
4. Smart Card Reader – XC2S100E-6PQ208I
- FPGA logic developed for Keypad Scanning
- Logic developed for Control and Configuration of Smart Card Interface
- Logic developed for Encryption of data
1. IF-DRX – XC3S5000-4FG900I
- Seven Channel high speed ADC Data Acquisition at 50Msps
- ADC Channels Gain and Offset Adjustment using Digital Techniques
- Interface to DPRAMs to Store High Speed ADC data
- Data Channel Bridge between Acquired ADC data and Local Bus
1. On-Board Memory Module (OMM) Ver 2.0 – XC3S1200E-4FG400I
- 8 Giga bytes Nand Flash Controller and Interface
- Local Bus Management
1. DSP-PCI – XC2V3000-6FG676C
- TigerSharc TS201 Link Port Interface
- Dual Channel high speed ADC data Acquisition
- Digital ADC offset and gain correction
- 32 bit FPDP Port
- 64 Channel LVDS Port
- 6 Channel DMA Interface to TS201
- DSP Cluster Bus Management
- Interrupt Handling
- DSP Co-processing block
- Switch Fabric Implementation for communication between blocks
2. IQ Card – XQ2V3000-4BG728N
- Designed on 3M GATES FPGA – XQ2V3000-4BG728N
- 2 Video input signals I & Q
- Analog to digital conversion using the ADS-949
- Computes the parameters to correct the imbalance between I & Q, corrects the imbalance (Required algorithm implemented in
- FPGA) and sends out the corrected I & corrected Q data (algorithm implemented in FPGA)
- 64 Channel LVDS Port
- Computes the absolute value from I corrected & Q corrected, compares against the threshold levels, which are inputs to this card and depending on the comparison, computes the clutter counts
- Clutter counts are made available on the data bus
- I corrected and Q corrected data are buffered and are output from the card
1. IF-DRX – Virtex 4-FX60
- On-chip PPC405 Instantiated (One No)
- External 64Mbytes of SDRAM interface
- External 64Mbytes of FLASH interface
- On-chip Rocket IO Channels (2 Nos)
- On-chip Gigabit Ethernet MAC (2 Nos)
- Serial FPDP Interface
- SERDES 16 bit 4 Channels
- VME Bus Controller (Master/Slave)
- LVDS Interface 12 Channels (8 RX and 4 TX)
1. DEMODULATOR – Virtex 6 – XC6VSX315T-1FFG1156I
- 2M x 36 bit of SRAM as a system memory
- 256Mb of flash memory as Configuration/application memory
- 2 x 1 Aurora interface
- Two Gigabit Ethernet ports
- One USB-UART port
- Accelerometer Interface
- Custom IO’s lines for gain setting and SPI implementation
- Load current measurement
2. CONTROL UNIT – Virtex 6 – XC6VSX315T-1FFG1156I
- 2M x 36 bit of SRAM as a system memory
- 256Mb of flash memory as Configuration/application memory
- 2 x 1 Aurora interface
- Two Gigabit Ethernet ports
- One USB-UART port
- Accelerometer Interface
- Custom IO’s lines for gain setting and SPI implementation
- Load current measurement
- 9 LVDS Pairs
1. Data Acquisition System – Spartan 6 – XC6SLX45T-2FGG484I
- 8 Meg x 16 x 8 bank DDR3 SDRAM
- 16M x 16 bit flash memory as Configuration/application memory
> One Gigabit Ethernet ports - One USB-UART port
- 28 simultaneous capture ADC channels with sampling rate of upto 1MSPS
- 2 x 1 Aurora interface
- On board ambient temperature measurement
- Load current measurement
2. Audio Test System – Spartan 6 – XC6SLX45T-2FGG484I
- 8 Meg x 16 x 8 bank DDR3 SDRAM
- 16M x 16 bit flash memory as Configuration/application memory
- One Gigabit Ethernet ports
- One USB-UART port
- 28 simultaneous capture ADC channels with sampling rate of upto 1MSPS
- 2 x 1 Aurora interface
- On board ambient temperature measurement
- Load current measurement
Projects
Description
Controller for Q-bus, a 16 bit parallel bus meant for data transfer between the Radar Computers in fighter aircraft. This controller is implemented on Xilinx’s FPGA device with 13K gates. The data transfer rate achieved is 2K words per second. This Q-bus controller is interfaced with the Intel 486DX2 processor and the processor can access the on-chip register to configure the controller to master or slave mode. In the slave mode, the controller receives the data and stores into Dual Port RAM. The processor will access the other side of the RAM to read the data.
The Q-bus controller has the following features
- Self-test of all the bus signals
- Data parity generation and checking
- On-chip registers to read the detected errors on the Q-bus during data transfer
- On-chip register to get the source of interrupt
- Interrupt logic
Development |
|
| PLD | FPGA, XC4013E, Xilinx |
| Design Language | VHDL |
| EDA tool | Xilinx Foundation series, version 2.1i |
| Simulation | Functional simulation using Active HDL simulator |
Description
Controller for handling 40 discrete inputs and 40 discrete outputs. This controller is interfaced with the part of the board designed to handle the discrete inputs and outputs. This board has Intel’s 486 processor. The controller has on-chip registers to handle interrupts to the processor. The design is implemented on Xilinx FPGA device of 5K gates density.
Development |
|
| PLD | FPGA, 4005E, Xilinx |
| Design Language | VHDL |
| EDA tool | Xilinx Foundation series, version 2.1i |
| Simulation | Functional simulation using Active HDL simulator |
Description
Implemented on Xilinx FPGA, the frequency to digital converter (FDC) provides digital data of the input frequency signal. The FDC has 16-bit and 12-bit counters and uses 1MHz free running clock as reference. The frequency measurement range is from 35Hz to 24 KHz, with accuracy of ± 5Hz. The FDC design is part of processor module in the control unit for aircraft, which interfaces to various sensors like thermocouple, Pressure transducers, turbine spool speed sensors, displacement sensors (LVDT, RVDT). These sensor output signals are converted to frequency domain by the signal conditioning block of the control unit. The FDC chip converts these frequency signals to digital domain and provides interface to processor to read this digital data. The FDC has fourteen frequency inputs.
Development |
|
| PLD | FPGA, 4005E, Xilinx |
| Design Language | VHDL |
| EDA tool | Xilinx Foundation series, version 2.1i |
| Simulation | Functional simulation using Active HDL simulator |
Description
The control logic designed to interface expansion module designed for Handspring handheld computer. The expansion module is interfaced to sensor board. The control logic reads and stores the image data captured by the image sensor module into the DRAM memory and allows the host computer to access this data. The software application in flash memory will process the image data and displays on the LCD of the handheld computer.
The control logic chip implements the following
- Decode logic to interface to expansion slot of the handheld
- Flash memory interface
- SDRAM and EDO DRAM controller
- Master I2C controller to program the image sensor chip
Development |
|
| PLD | CPLD, XC95288XL, Xilinx |
| Design Language | VHDL |
| EDA tool | WebPack ISE, Project Navigator release 4.1 |
| Simulation | Model Sim for Simulation VHDL test bench and test vectors |
Description
The PCI add-in card has control logic to interface with PCI bus target chip and to generate the control signals required to access the I/O devices. The control logic in implemented on CPLD with 128 macro cells.
Development |
|
| PLD | CPLD, CY37128, Cypress Semiconductors |
| Design Language | VHDL |
| EDA tool | Warp 4.0 |
| Simulation | Model Sim for Simulation VHDL test bench and test vectors |
Description
The control logic interfacing the PC card bus and the pulse delay generation circuitry. The PC card has frequency synthesizer IC, which is programmable through I2C bus protocol. The control logic has I2C master controller to interface with the frequency synthesizer and other I2C devices in the board.
Development |
|
| PLD | CPLD, XC95288XL, Xilinx |
| Design Language | VHDL |
| EDA tool | WebPack ISE, Project Navigator release 4.1 |
| Simulation | Model Sim for Simulation VHDL test bench and test vectors |
Description
This PCI add-in card is designed to program the frequency generator instrument which is programmable using the BCD interface it provides. The control logic in the card interfaces to the PCI target chip and SRAM memory. The user can store the BCD data into the SRAM and can initiate cycle to read SRAM data and put the BCD data to the frequency generator instrument. The control logic also interfaces with DAC to generate the DC voltage required for the setting the voltage level of frequency signal of the frequency generator.
Development |
|
| PLD | CPLD, XC95288XL, Xilinx |
| Design Language | VHDL |
| EDA tool | WebPack ISE, Project Navigator release 4.1 |
| Simulation | Model Sim for Simulation VHDL test bench and test vectors |
Description
This design on CPLD is implemented to provide the memory resource sharing for two modules, one based on Intel 486 processor and the other module based on Intel 87C196 microcontroller. The microcontroller module has interfaces to four types of serial bus protocols – MIL-STD1553B, ARINC- 429, RS-422 and RS232. The control logic interfaces all the four serial bus controllers and provides SRAM interface for the microcontroller to store the serial bus data. The arbitration logic in the CPLD using the interrupt logic and data/address bus buffer control logic allows the SRAM to be accessed by the 486 module.
Development |
|
| PLD | EPLD, EPM7128, Altera |
| Design Language | AHDL (Altera Hardware Design Language) |
| EDA tool | MAX+PLUS II for design, synthesis and simulation |