ASIC Projects

Description
Controller for Q-bus, a 16 bit parallel bus meant for data transfer between the Radar Computers in fighter aircraft. This controller is implemented on Xilinx’s FPGA device with 13K gates. The data transfer rate achieved is 2K words per second. This Q-bus controller is interfaced with the Intel 486DX2 processor and the processor can access the on-chip register to configure the controller to master or slave mode. In the slave mode, the controller receives the data and stores into Dual Port RAM. The processor will access the other side of the RAM to read the data.

The Q-bus controller has the following features

  • Self-test of all the bus signals
  • Data parity generation and checking
  • On-chip registers to read the detected errors on the Q-bus during data transfer
  • On-chip register to get the source of interrupt
  • Interrupt logic
Development
PLD FPGA, XC4013E, Xilinx
Design Language VHDL
EDA tool Xilinx Foundation series, version 2.1i
Simulation Functional simulation using Active HDL simulator

Description
Controller for handling 40 discrete inputs and 40 discrete outputs. This controller is interfaced with the part of the board designed to handle the discrete inputs and outputs. This board has Intel’s 486 processor. The controller has on-chip registers to handle interrupts to the processor. The design is implemented on Xilinx FPGA device of 5K gates density.

Development
PLD FPGA, 4005E, Xilinx
Design Language VHDL
EDA tool Xilinx Foundation series, version 2.1i
Simulation Functional simulation using Active HDL simulator

Description
Implemented on Xilinx FPGA, the frequency to digital converter (FDC) provides digital data of the input frequency signal. The FDC has 16-bit and 12-bit counters and uses 1MHz free running clock as reference. The frequency measurement range is from 35Hz to 24 KHz, with accuracy of ± 5Hz. The FDC design is part of processor module in the control unit for aircraft, which interfaces to various sensors like thermocouple, Pressure transducers, turbine spool speed sensors, displacement sensors (LVDT, RVDT). These sensor output signals are converted to frequency domain by the signal conditioning block of the control unit. The FDC chip converts these frequency signals to digital domain and provides interface to processor to read this digital data. The FDC has fourteen frequency inputs.

Development
PLD FPGA, 4005E, Xilinx
Design Language VHDL
EDA tool Xilinx Foundation series, version 2.1i
Simulation Functional simulation using Active HDL simulator

Description
The control logic designed to interface expansion module designed for Handspring handheld computer. The expansion module is interfaced to sensor board. The control logic reads and stores the image data captured by the image sensor module into the DRAM memory and allows the host computer to access this data. The software application in flash memory will process the image data and displays on the LCD of the handheld computer.

The control logic chip implements the following

  • Decode logic to interface to expansion slot of the handheld
  • Flash memory interface
  • SDRAM and EDO DRAM controller
  • Master I2C controller to program the image sensor chip
Development
PLD CPLD, XC95288XL, Xilinx
Design Language VHDL
EDA tool WebPack ISE, Project Navigator release 4.1
Simulation Model Sim for Simulation VHDL test bench and test vectors

Description
The PCI add-in card has control logic to interface with PCI bus target chip and to generate the control signals required to access the I/O devices. The control logic in implemented on CPLD with 128 macro cells.

Development
PLD CPLD, CY37128, Cypress Semiconductors
Design Language VHDL
EDA tool Warp 4.0
Simulation Model Sim for Simulation VHDL test bench and test vectors

Description
The control logic interfacing the PC card bus and the pulse delay generation circuitry. The PC card has frequency synthesizer IC, which is programmable through I2C bus protocol. The control logic has I2C master controller to interface with the frequency synthesizer and other I2C devices in the board.

Development
PLD CPLD, XC95288XL, Xilinx
Design Language VHDL
EDA tool WebPack ISE, Project Navigator release 4.1
Simulation Model Sim for Simulation VHDL test bench and test vectors

Description
This PCI add-in card is designed to program the frequency generator instrument which is programmable using the BCD interface it provides. The control logic in the card interfaces to the PCI target chip and SRAM memory. The user can store the BCD data into the SRAM and can initiate cycle to read SRAM data and put the BCD data to the frequency generator instrument. The control logic also interfaces with DAC to generate the DC voltage required for the setting the voltage level of frequency signal of the frequency generator.

Development
PLD CPLD, XC95288XL, Xilinx
Design Language VHDL
EDA tool WebPack ISE, Project Navigator release 4.1
Simulation Model Sim for Simulation VHDL test bench and test vectors

Description
This design on CPLD is implemented to provide the memory resource sharing for two modules, one based on Intel 486 processor and the other module based on Intel 87C196 microcontroller. The microcontroller module has interfaces to four types of serial bus protocols – MIL-STD1553B, ARINC- 429, RS-422 and RS232. The control logic interfaces all the four serial bus controllers and provides SRAM interface for the microcontroller to store the serial bus data. The arbitration logic in the CPLD using the interrupt logic and data/address bus buffer control logic allows the SRAM to be accessed by the 486 module.

Development
PLD EPLD, EPM7128, Altera
Design Language AHDL (Altera Hardware Design Language)
EDA tool MAX+PLUS II for design, synthesis and simulation

Services

HARDWARE
  • Board designs (digital, analog and mixed signal) using various microprocessors and micro-controllers, RISC processors, DSPs etc
  • FPGA/PLD designs incorporating Xilinx, Lattice, Cypress, Altera devices
  • IP core development and ASIC designs using VHDL, Verilog tools
SOFTWARE
  • Real-Time Application design, development, testing and implementation
  • Device drivers development for various devices like MIL1553, ARINC-429, Intel processor family, ARM processor family,
  • PowerPC processor family, related peripheral controllers for SDRAM, DDR RAM, SCSI, Ethernet, USB, Graphics
  • Board Support Packages development and porting on popular Real Time operating Systems like LynxOS, VxWorks
  • Cross Platform Development and OS Porting
  • Expertise in Assembly languages like Intel, Motorola, Universal boot loader, C/C++, OS: Windows, Linux, RTLinux, VxWorks, LynxOS, INTREGRITY

System Design

  • System design, analysis, re-engineering, downsizing, prototyping, ruggedisation and obsolescence
  • System interface design and implementation including cabling and installation
  • Mechanical enclosure design engineering and fabrication support